ATMEGA32L-8PJ【PDF 8/21 页】IC MCU AVR 32K 5V 8MHZ 40-DIP

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Sheet目录1905

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2503QS–AVR–02/11

ATmega32(L)

Errata

ATmega32, rev. A

to F

First Analog Comparator conversion may be delayed

Interrupts may be lost when writing the timer registers in the asynchronous timer

IDCODE masks data from TDI input

Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request.

First Analog Comparator conversion may be delayed

If the device is powered by a slow rising V

CC, the first Analog Comparator conversion will

take longer than expected on some devices.

Problem Fix/Workaround

When the device has been powered or reset, disable then enable theAnalog Comparator

before the first conversion.

Interrupts may be lost when writing the timer registers in the asynchronous timer

The interrupt will be lost if a timer register that is synchronous timer clock is written when the

asynchronous Timer/Counter register (TCNTx) is 0x00.

Problem Fix/Workaround

Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor

0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous-

Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx).

IDCODE masks data from TDI input

The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are

replaced by all-ones during Update-DR.

Problem Fix / Workaround

–

If ATmega32 is the only device in the scan chain, the problem is not visible.

–

Select the Device ID Register of the ATmega32 by issuing the IDCODE instruction or

by entering the Test-Logic-Reset state of the TAP controller to read out the contents

of its Device ID Register and possibly data from succeeding devices of the scan

chain. Issue the BYPASS instruction to the ATmega32 while reading the Device ID

Registers of preceding devices of the boundary scan chain.

–

If the Device IDs of all devices in the boundary scan chain must be captured

simultaneously, the ATmega32 must be the fist device in the chain.

Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt

request.

Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg-

ister triggers an unexpected EEPROM interrupt request.

Problem Fix / Workaround

Always use OUT or SBI to set EERE in EECR.

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